1. Field of the Invention
The present invention relates to a field effect transistor (FET), and more particularly to a method for producing a metal insulator semiconductor (MIS) FET in which an active region is surrounded by a thick insulating layer.
2. Description of the Prior Art
A MISFET can control a channel current flowing between a source and a drain by supplying a voltage to a gate electrode formed on a thin insulating film on a semiconductor substrate. A well-known metal-oxide semiconductor (MOS) FET is one kind of MISFET. For example, a number of MOSFETs are produced in a semiconductor chip for an integrated circuit. Active regions of the MOSFETs are formed in a semiconductor substrate and are isolated from each other by suitable isolation means, e.g., a thick insulating layer which is formed on a field region of the semiconductor substrate and surrounds each of the active regions. The thick insulating layer (i.e., a so-called field insulating layer) is also intended to prevent a parastic MOS effect and a parastic capacitance effect.
A method for producing the above-mentioned MOSFET is now explained with reference to FIGS. 1 and 2.
A silicon semiconductor substrate 1 is selectively oxidized to form a thick insulating layer (i.e., a field insulating layer) 2. Namely, silicon semiconductor substrate 1 is thermally oxidized to form a thin silicon dioxide layer (not shown) on substrate 1. A silicon nitride layer (not shown) is deposited on the thin silicon dioxide layer and is then selectively etched by a conventional photo-etching method. The portion of the silicon substrate 1 which is not covered by the silicon nitride layer is sufficiently thermally oxidized to form a thick insulating layer 2 of silicon dioxide. the silicon nitride layer and the thin silicon dioxide layer under it are removed by etching. Thus, the thick insulating layer 2 is located on a field region 3 and surrounds an active region 4 of the silicon substrate 1. The active region 4 of the silicon substrate 1 is slightly oxidized to form a thin insulating layer 5 of silicon dioxide.
Then a gate electrode 6 is formed on the thick insulating layer 2 and thin insulating layer 5 crossing the active region 4 and extending above the field region 3. The a conductive material (e.g., polycrystalline silicon) of the electrode 6 is deposited on the thick insulating layer 2 and the thin insulating layer 5 to form a conductive layer. A photoresist (not shown) is applied to the conductive layer, exposed by light passing through a photomask having a gate electrode pattern, and is developed to form a gate electrode photoresist pattern (not shown). The portion of the conductive layer which is not covered by the gate electrode photoresist pattern is removed by etching to form the gate electrode 6.
In order to form a source region S and a drain region D in the active region 4 of the silicon substrate 1, N-type or P-type impurities are introduced into the active region 4, except for a portion covered by the gate electrode 6, by an ion implantation method. Thereafter, an annealing treatment is carried out. A source electrode and a drain electrode (not shown) are formed in accordance with a conventional production method to obtain the MOSFET.
In the case of the above-mentioned production method, however, portions of the gate electrode 6 to be formed are undesirably etched on the inclined surface of thick insulating layer 2 and above the end portions of the active region 4, as illustrated in FIG. 1. Although the gate electrode pattern of the photomask comprises straight sides, constricted portions of the gate electrode photoresist pattern corresponding to a constricted portions 7 and 8 of the gate electrode 6 are formed due to a variation of the photoresist layer thickness and irregular reflection of the exposing light at the inclined surface of the thick insulating layer 2. Therefore, the constricted portions 7 and 8 of the gate electrode 6 are formed during the etching step. When the source region S and drain region D are formed, projecting portions of these regions are formed next to the constricted portions 7 and 8 of the gate electrode 6, with the result that the threshold voltage varies, the leakage current is increased, and the breakdown voltage between the source and drain is decreased. The above disadvantages become more serious when a MOSFET having a short width W gate electrode (FIG. 1) i.e., a short channel length, is produced. Such a MOSFET having a short channel length is not suitable for a high frequency device. Furthermore, since a photoresist having a high sensitivity is used in the formation of a narrow gate electrode, the constricted portions of the gate electrode photoresist pattern are formed more easily.